The present invention relates to a method of manufacturing a semiconductor device exhibiting reduced capacitance loading. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices comprising sub-micron dimensions and exhibiting high circuit speed.
Interconnection technology is constantly challenged to satisfy the ever increasing requirements for high density and performance associated with ultra large scale integration semiconductor devices. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit speed. As integrated circuits become complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the performance of multi-level interconnects is dominated by interconnect capacitance at deep sub-micron regimes, e.g., less than about 0.12 micron. The rejection rate due to integrated circuits speed delays in sub-micron regimes has become a limiting factor in fabrication.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an inter-layer dielectric (ILD) ranges from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constant expressed herein is based upon a value of one for a vacuum. In an effort to reduce interconnect capacitance, dielectric materials with lower values of permitivity have been explored. The expression xe2x80x9clow-kxe2x80x9d material has evolved to characterize materials with a dielectric constant less than about 3.9. One type of low-k material that has been explored are a group of flowable oxides which are basically ceramic polymers, such as hydrogen silsesquioxane (HSQ). Such polymers and their use are disclosed in, for example, U.S. Pat. No. 4,756,977 and U.S. Pat. No. 5,981,354. HSQ-type flowable oxides have been considered for gap filling between metal lines because of their flowability and ability to fill small openings. HSQ-type flowable oxides have been found to be vulnerable to degradation during various fabrication steps, including plasma etching. Methods involving plasma treatment have been developed to address such problems attendant upon employing HSQ-type flowable oxides as a gap filling layer, as in the U.S. Pat. No. 5,866,945 and U.S. Pat. No. 6,083,851.
There are several organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD. As used throughout this disclosure, the term xe2x80x9corganicxe2x80x9d is intended to exclude HSQ type materials, e.g., flowable oxides and ceramic polymers, which are not true organic materials. Organic low-k materials which offer promise are carbon-containing dielectric materials such as FLARE 2.0(trademark) dielectric, a poly(arylene)ether available from Allied Signal, Advanced Microelectronic Materials, Sunnyvale, Calif., Black-Diamond(trademark) dielectric available from Applied Materials, Santa Clara, Calif., BCB (divinylsiloxane bisbenzocyclobutene) and Silk(trademark) an organic polymer similar to BCB, both available from Dow Chemical Co., Midland, Mich.
In attempting to employ such carbon-containing low-k materials in interconnect technology, as for gap filling or as an ILD, it was found that their dielectric constant became undesirably elevated as a result of subsequent processing. For example, the dielectric constant of BCB was found to increase from about 2.6 to greater than about 4. It is believed that such an increase occurs as a result of exposure to an oxygen (O2) plasma stripping technique employed to remove photoresist material after formation of an opening in a dielectric layer as, for example, a via hole or dual damascene opening for interconnecting of metal features on different metal levels. U.S. Pat. No. 6,030,901 discloses a method of addressing such a degradation problem by stripping a photoresist mask by using a H2N2 plasma.
There exists a need for methodology enabling the use of low-k carbon-containing dielectric materials as an ILD in high density, multi-level interconnection patterns. There exist a particular need for methodology enabling the use of such low-k materials while avoiding their degradation from various fabrication steps subsequent to deposition.
An advantage of the present invention is a method of manufacturing a semiconductor device exhibiting reduced parasitic RC time delays employing carbon-containing (i.e., organic) dielectric materials having a low dielectric constant.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming an organic layer having an exposed surface; and treating the exposed surface with a plasma containing a source of hydrogen, such as ammonia (NH3), and nitrogen (N2).
Embodiments of the present invention comprise depositing an ILD of an organic material, such as SiCOH containing Si-H bonds, and treating the surface with a NH3/N2 plasma. Subsequently, a damascene opening is formed in the ILD exposing internal surfaces and the exposed internal surfaces are also treated with the NH3/N2 plasma. After plasma treating the internal surfaces, the damascene opening is filled with a metal, and the overburden is planarized, as by chemical-mechanical polishing (CMP), leaving an exposed upper surface of the ILD. The exposed upper surface of the ILD is also treated with the NH3/N2 plasma before capping layer deposition. Plasma treatment of the organic ILD in accordance with the present invention at various times during the interconnect process substantially prevents or significantly reduces degradation of the organic ILD, such as an undesirable increase in the dielectric constant, undesirable shrinkage and an undesirable shifting in the reflective index, as a result of subsequent processing steps, such as O2 ashing, etching, exposure to elevated temperature and/or exposure to various chemicals, e.g., CMP slurries.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded and illustrative in nature, and not as restrictive.